1. Field of the Invention
The present invention generally relates to gate arrays and, more particularly, the present invention relates to gate arrays which are improved so that a time period required for development of a semiconductor integrated circuit device can be shortened. The present invention further relates to a manufacturing method of a semiconductor integrated circuit device using such a gate array.
2. Description of the Background Art
A gate array is a chip on which circuit elements (basic cells) such as transistors for constituting a logic gate are regularly arranged. Gate arrays are manufactured and stocked in advance. A manufactured and stocked gate array is called a "master slice". A gate array is provided with an interconnection pattern designed for each customer's circuit to be finished as an LSI at the end. Designing of the interconnection pattern (a customized design) is usually carried out according to a procedure as shown in FIG. 1, using an automatic layout design. An interconnection pattern of a basic circuit such as each kind of logic gate, a flip-flop and so on is designed (referred to as a microcell) and registered in a library in advance and then automatically laid out and interconnected.
Examples of lay-out forms of a master slice of a gate array are shown in FIGS. 2 and 3. An island array shown in FIG. 2 is often found in a bipolar gate array. A continuous column array shown in FIG. 3 is often used for a CMOS gate array.
Referring to FIGS. 2 and 3, a plurality of basic cells 1 are arranged regularly in a chip T. Basic cells 1 are connected to each other by an interconnection process after a contacting process according to a circuit to be constructed, thereby forming a semiconductor integrated circuit device.
In these figures, a region where there is no basic cell 1 is called a "channel region" 2 where interconnecting lines are formed for connecting basic cells 1. Peripheral cells 3 are provided in the periphery of chip T.
The semiconductor integrated circuit device is formed by providing a first interconnecting line in the channel region 2, then forming an interlayer insulating film over the first interconnecting line, and further providing a second interconnecting line over the interlayer insulating film.
The use of a gate array in forming a semiconductor integrated circuit is intended for reducing the time period of its development. There has been an increasing need for a further reduction in this time period in recent years.
In order to meet such a need, an improved gate array has been developed for connecting basic cells by a single interconnection layer instead of two interconnection layers. A single interconnection layer reduces necessary masking processes, which makes it possible to shorten the period for the development.
However, such a gate array has a difficulty that a chip area is increased due to a decrease in the interconnecting efficiency, which results in an increased cost. Accordingly, although a gate array having a single interconnection layer can be used for testing the operation, it is not suitable for practical manufacture.